The dual channel memory architecture’s working has interested me so much. I was confused by the fact that what benefit would you get if you’re desired memory addresses are mapped in only channel. But, today after reading the Intel 915G chipset memory configuration guide, I got to know that in symmetrical dual channel environment, memory is interleaved. It is interleaved at the interval of every cache line (usually 128 bytes in Pentium 4). So my solution lies in population of memory
Thanx to Gautam, who pointed out that I should refer to GMCH specs.