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Single Dual Core CPU and Dual Single Core CPUs

Filed under: C0D, Research — abbe @ 0146

Well, yesterday I was thinking whether dual core CPUs are better or dual single core CPUs are better ? I’m thinking from the Intel‘s perspective, since I’ve only Intel stuff, though its my dream to try out other manufacturer’s hardware also ;-). So then I called Gautam, and like me he also suggested that dual single core CPUs perform better than single dual core CPU. Why, I’m thinking so because dual core CPUs just have two execution engines ( as compared to, two architectural states on top of single execution engine in case of hyper-threading technology ), but share the same FSB, so if two cores are executing tasks which require memory (not present in CPU caches), which means both cores require simultaneous memory access, and is not possible, so one core has to stall.

Anyways, I posted this to comp.arch Usenet newsgroup, and there somebody reminded me that AMD has also gone Multicore. Then I came to know about HyperTransport, and its NUMA kind of technology.

From the discussion, I’d there I concluded that Dual Core CPUs should be preferred in HyperTransport based systems, and in Shared FSB based systems Dual Single Core CPUs should be preferred. You can read that discussion for more information.

Thanks to Mayank, I got introduced to 2 new terms: CMP, and SMT.


How Dual Channel memory works ?

Filed under: C0D, Research — abbe @ 1805

The dual channel memory architecture’s working has interested me so much. I was confused by the fact that what benefit would you get if you’re desired memory addresses are mapped in only channel. But, today after reading the Intel 915G chipset memory configuration guide, I got to know that in symmetrical dual channel environment, memory is interleaved. It is interleaved at the interval of every cache line (usually 128 bytes in Pentium 4). So my solution lies in population of memory

Thanx to Gautam, who pointed out that I should refer to GMCH specs.

Checkout Intel 915G/915GV/910GL Express Chipset memory configuration guide

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